PhD Position F/M Making Caches Predictable: Bounded Lifetime Monitoring and Management for Real-Time Systems

Context
The PhD will be led by Inria Rennes, in close collaboration with RPTU and Inria Lille under the ANR PRCI CoCoDaLi
Additional information about the city and the university
Rennes is a vibrant and student-friendly city in northwestern France. The city has a thriving student culture, with plenty of bars, restaurants, cultural events, and an affordable cost of living. Additionally,
Rennes is evaluated as one of the best cities to live in Europe
.
Rennes is home to the University of Rennes, one of the largest universities in France. The University of Rennes has a strong focus on innovation and technology. It is home to many world-renowned research institutes, including INSA, IRISA, and INRIA Rennes. These institutes offer a wide range of Ph.D. programs in computer science, covering various topics such as artificial intelligence, machine learning, data science, and hardware and software engineering. Ph.D. students in Rennes benefit from close relationships with faculty and access to state-of-the-art facilities. The students also have the opportunity to collaborate with leading researchers worldwide.
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Assignment
Context
Caches are one of the main reasons modern processors are fast — and one of the main reasons real-time systems are hard to certify.
In safety-critical domains such as autonomous vehicles, avionics, robotics, industrial control, and cyber-physical systems, software must not only produce the correct result; it must also do so within a guaranteed deadline. To provide such guarantees, engineers need reliable bounds on the Worst-Case Execution Time, WCET, of each task. Yet caches make this difficult: they evict data that will be needed later, and create interference between tasks or even within the same task.
Today, much of this interference is treated pessimistically. Timing analyses often assume worst-case cache behavior because they cannot precisely know which cache blocks are hits or misses. This pessimism leads to overestimated WCET bounds, reduced schedulability, underused hardware resources, and more expensive system designs.
The goal of this PhD is to design mechanisms that turn caches from a source of unpredictability into a resource that can be controlled, reasoned about, and exploited more efficiently in real-time systems.
Main activities
Research Activities
This PhD focuses on the design, analysis, implementation, and evaluation of predictable cache management mechanisms for real-time systems, with the goal of improving execution efficiency while enabling tighter and more reliable WCET bounds.
To achieve that, we will propose low-overhead, bounded, and analyzable mechanisms for monitoring memory block lifetimes and cache management mechanisms to reduce WCET pessimism. We will investigate hardware-assisted and software-assisted mechanisms to monitor the runtime evolution of memory object lifetimes in the cache hierarchy. The monitoring mechanisms must have constant and bounded overhead, independent of the cache state, so that they remain compatible with WCET analysis. We will design runtime cache management mechanisms that enforce allocation and scheduling decisions, at different granularities. We will evaluate these mechanisms in terms of predictability, implementation complexity, compatibility with memory hierarchies and cache coherence protocols, and performance impact. The PhD will include a systematic analysis of the trade-offs between monitoring granularity, management granularity, runtime overhead, WCET pessimism, and system performance.
The research will bridge offline scheduling, cache allocation, and runtime enforcement to improve both predictability and efficiency in real-time systems.
Skills
Candidate Profile
The candidate should have a strong background in one or more of the following areas:
computer architecture
cache and memory hierarchy design
real-time systems
operating systems or runtime systems
WCET analysis
Good programming skills are expected, preferably in C/C++, and Python.
Experience with architectural simulators, such as GEM5, and low-level systems programming would be an advantage.
Languages
: proficiency in written English and fluency in spoken English.
The interviews for the PhD will be in English.
Relational skills
: the candidate will work in a research team, where regular meetings will be set up. The candidate has to be able to present the progress of their work in a clear and detailed manner.
Other values appreciated
: Open-mindedness, strong integration skills, and team spirit.
Most importantly, we seek highly motivated candidates.