Post-Doctoral Research Visit F/M Reliability Assessment and Fault-Tolerance Methods for Cloud FPGA and PIM Accelerators

Context
Context and Motivation
The TARAN research group at INRIA/IRISA in Rennes, France, invites applications for a postdoctoral researcher in the area of reliability assessment and fault tolerance for modern hardware accelerators. The position is part of ongoing European, international, and national research projects conducted with academic and industrial partners. The postdoctoral researcher will focus on accelerator platforms that are relevant for Cloud deployment, particularly FPGA-based accelerators and processing-in-memory (PIM).
Specialized accelerators are increasingly adopted in Cloud infrastructures to execute compute- and data-intensive workloads efficiently [1]. FPGA accelerators offer reconfigurability and high performance per watt, while PIM computing architectures aim to reduce the cost of data movement by placing computation close to memory [2]. These platforms are especially relevant for workloads with substantial memory traffic, including artificial intelligence, data analytics, and signal-processing applications.
Despite this potential, relatively few studies have investigated the reliability of FPGA accelerators in a Cloud context. Similarly, much of the existing reliability literature on PIM computing concentrates on emerging memory technologies, such as RRAM, STT-MRAM, or PCM, and relies on simulations or simplified prototypes [3, 4]. Such studies provide useful insights but do not fully address the reliability challenges of accelerators that will be deployed in large scale systems. A detailed understanding of fault sources, fault propagation, and application-level effects is therefore needed before these architectures can be used confidently in demanding computing environments. Conventional replication-based solutions, such as duplication or triple modular redundancy, may impose prohibitive performance, area, and energy costs. The project will consequently investigate efficient, targeted fault-tolerance methods grounded in a detailed characterization of accelerator vulnerabilities.
Research Scope
The postdoctoral researcher will develop and apply a comprehensive methodology for evaluating the reliability of FPGA accelerators and PIM. The work will combine experimental and simulation-based approaches across several abstraction levels. The methodology for validation will use fault-injection campaigns at microarchitectural and software levels. For PIM architectures, the evaluation will use representative benchmark suites, such as PrIM, together with additional workloads selected according to the target architecture. For FPGA accelerators, the work will build on applications developed in the TARAN team national projects, with a particular emphasis on AI workloads. The objective is to characterize fault sensitivity, identify critical hardware and software resources, quantify the propagation of faults to workload-level outcomes, and assess practical mechanisms that improve robustness with limited overhead.
The expected outcomes include reliability-evaluation methodologies, fault models and experimental datasets, cross-layer analysis tools, and efficient fault-mitigation strategies for Cloud-oriented FPGA and PIM accelerators. The postdoctoral researcher will work closely with the TARAN team and project partners and will contribute to the development of innovative research proposals and publications in this area.
Relevant Team Expertise
The team has established experience in reliability assessment, cross-layer reliability analysis, efficient fault-injection methodologies, and selective protection of AI accelerators. This postdoctoral project will extend these strengths toward FPGA-based Cloud accelerators and commercially relevant PIM systems.
Selected Team Reference Publications
Roquet, F. F. dos Santos, P. Rech, M. Traiola, O. Sentieys and A. Kritikakou, "Cross-Layer Reliability Evaluation and Efficient Hardening of Large Vision Transformers Models," 2024 61st ACM/IEEE Design Automation Conference (DAC)
M. Traiola, et al., Impact of High-Level-Synthesis on Reliability of Artificial Neural Network Hardware Accelerators, IEEE Transactions on Nuclear Science, 2024.
B. Tonetto, et al., "ENFOR-SA: End-to-end Cross-layer Transient Fault Injector for Efficient and Accurate DNN Reliability Assessment on Systolic Arrays," 2026 IEEE 44th VLSI Test Symposium (VTS)
F. d. Santos et al., "Improving Deep Neural Network Reliability via Transient-Fault-Aware Design and Training," in IEEE Transactions on Emerging Topics in Computing, 2025
B. Tonetto, et al. Scalable Reliability Assessment of DNNs through Simultaneous Fault Injection. IEEE/ACM Design Automation Conference, DAC 2026
R. B. Tonetto, et al. The Anatomy of a Misprediction: Tracking Terrestrial and Orbital Radiation-Induced Errors in Systolic Arrays. SC 2026 - International Conference for High Performance Computing, Networking, Storage, and Analysis, Nov 2026, Chicago, United States
Other publications from TARAN:
https://team.inria.fr/taran/publications/
Other References
[1] C. Bobda, et al. The Future of FPGA Acceleration in Datacenters and the Cloud. ACM Trans. Reconfigurable Technol. Syst. 15, 3, Article 34 (September 2022)
[2] A. Sebastian, et al. Memory devices and applications for in-memory computing. Nat. Nanotechnol. 15, 529–544 (2020).
[3] Z. Yan, et al. On the Reliability of Computing-in-Memory Accelerators for Deep Neural Networks. System Dependability and Analytics. Springer Series in Reliability Engineering. Springer, Cham.
[4] J. Jung. Reliable Processing-in-Memory. The University of Texas at Austin, Electrical and Computer Engineering, Thesis (May 2025).
Assignment
Research Scope
The postdoctoral researcher will develop methods and tools to evaluate and improve the reliability of cloud-oriented accelerators, with a focus on FPGA platforms and practical PIM architectures.
Possible research directions include:
Reliability evaluation of FPGA accelerators and PIM architectures under representative Cloud workloads.
Characterization of fault sources and vulnerable resources in memory, logic, interconnects, and control structures.
Cross-layer analysis of fault propagation from hardware resources to application-level outcomes.
Simulation-based fault injection at microarchitectural and software levels.
Development of fault models, reliability metrics, and experimental methodologies suitable for commercially relevant accelerators.
Design and assessment of efficient fault-mitigation techniques that avoid the excessive cost of full duplication or triple modular redundancy.
Selective protection, architecture-level mitigation, software-level resilience techniques, and cross-layer fault-tolerance strategies.
Both
theoretical
and
experimental
contributions are welcome, depending on the candidate's expertise.
Main activities
Role and Responsibilities
This is a research-focused academic position, not an engineering or support role.
Expected duties include:
conducting original research and publishing in leading venues
supervising and mentoring
PhD students and Master’s interns
participating in
European and National research projects
, including:
research contributions in collaborative work packages
project reporting and deliverables
contribution to project design and writing for future calls
interaction with industrial and academic partners
presenting results at international conferences and consortium meetings
Environment and Funding
Institution:
INRIA/IRISA, TARAN team, Rennes, France.
Funding:
The position is funded through ongoing European and national research projects. Travel related to project activities and scientific dissemination will be covered according to project and institutional rules.
Collaboration:
The researcher will work with international academic and industrial partners involved in accelerator reliability, Cloud computing, and dependable computing systems.
Duration:
Up to 24 months, subject to the applicable funding framework and institutional conditions.
Start date:
2026, with flexibility depending on administrative procedures and candidate availability.
Applications will be reviewed on a rolling basis until the position is filled.