Pilot Line PDK & Design Enablement Lead

Pilot Line PDK & Design Enablement Lead
SAL - Silicon Austria Labs
Villach, Austria
From € 70.000 per year gross
In the Position as Staff Research Engineer you are responsible for the central PDK function across SAL’s technology platforms and pilot-line activities. You ensure that PDK content, models, verification flows, documentation, and release processes are consistent, traceable, and aligned with fabrication capabilities—enabling reliable design-to-fab handshakes for internal teams and open-access users (with a strong relevance for integrated photonics and related quantum/MEMS device concepts).
Your future tasks include:
PDK strategy & roadmap: define and maintain a consolidated PDK roadmap (priorities, maturity targets, releases) aligned with platform and fabrication evolution;
PDK governance & release management: establish a structured release process (versioning, release notes, change control, qualification evidence, deprecation rules) and ensure predictable delivery for users;
Design-to-fab interface: act as the interface between designers and fabrication teams to align layer definitions, design rules, tolerances, process assumptions, sign-off criteria, and handover packages;
PDK content quality: own quality of PDK deliverables such as DRC/LVS/PEX flows (as applicable), models, corners/variability knobs, examples, and user documentation;
Validation & calibration: coordinate validation and calibration plans with measurement/metrology and process teams; ensure model updates are evidence-based and traceable to wafer data;
EDA and enablement flows: maintain compatibility with relevant EDA toolchains; provide reference flows, templates, and automation where beneficial (build/release tooling, regression checks);
User support & enablement: support internal teams and selected external open-access users (onboarding, requirements clarification, feedback capture) and translate user needs into backlog items;
Documentation & know-how management: ensure strong documentation discipline and coordinate what can be shared externally vs what must be protected, in collaboration with responsible functions.
Your profile:
Strong experience (min. 8+ years) in PDK development and design enablement (verification flows, models, documentation, releases) in a semiconductor/photonics/MEMS-related environment;
MSc/PhD in EE, Physics, Photonics, Microsystems, or comparable;
Solid understanding of the design–fabrication interface and how process variability impacts models, rules, and design margins;
Hands-on experience with EDA ecosystems and PDK integration; scripting/automation skills (e.g., Python/TCL) are a strong plus;
Experience working with wafer data for model calibration/validation and structured change control;
Strong communication skills and ability to coordinate across a matrix organization (design, process teams, metrology, external users);
Fluent English; German is a plus.
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SAL - Silicon Austria Labs